Arsenic-doped epitaxial source/drain regions for NMOS

US12094881B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Anand S. Murthy · Beaverton, US
• Ryan Keech · Portland, US
• Nicholas G. Minutillo · Beaverton, US
• Ritesh Jhaveri · Portland, US

Key dates

• Filing date: Feb 10, 2023
• Grant date: Sep 17, 2024
• Expiry date: Feb 10, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0158

Abstract

Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.