Efficient decoding schemes for error correcting codes for memory devices
US12095481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.