Memory device with internal processing interface
US12099455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Aug 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7821
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.