Memory block utilization in memory systems
US12099734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Aug 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.