Instruction and logic for sum of square differences
US12099838B2 · kind B2 · utility
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1References
17Claims
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Key dates
| Filing date | Dec 23, 2020 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Dec 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes: a fetch circuit to fetch instructions, the instructions including a sum of squared differences (SSD) instruction; a decode circuit to decode the SSD instruction; and an execution circuit to, during an execution of the decoded SSD instruction, generate an SSD output vector based on a plurality of input vectors, the SSD output vector including a plurality of squared differences values. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.