Dynamic allocation of pattern history table (PHT) for multi-threaded branch predictors
US12099844B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | May 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exemplary branch predictor apparatus comprises a Pattern History Table (PHT) configured with a PHT allocation multiplexer/demultiplexer (PAMD) configurable to output a prediction logically selected from a portion of the PHT entries selectively allocated among a plurality of threads. The PHT entries may be allocated among a plurality of threads based on control bits read from a Control and Status Register (CSR) at system initialization. The branch predictor may govern a plurality of threads fetching instructions from an address selected from a Branch Target Buffer (BTB) entry indexed based on a per-thread Program Counter (PC) or a PHT entry indexed based on a per-thread Global History Register (GBHR). The PHT entries may be saturating binary counters. The saturating counters may be two-bit counters. An exemplary implementation may permit reduced misprediction rate, increased throughput, or reduced energy consumption resulting from increased allocation of PHT entries to more branch-intensive threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.