Chip heat dissipation structure, chip structure, circuit board and supercomputing device
US12100639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2021 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | May 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present application relates to a chip heat dissipation structure, a chip structure, a circuit board, and a supercomputing device, and the chip heat dissipation structure includes: a plating layer covering a wafer of the chip; where the plating layer includes a first metal layer, a second metal layer, and a third metal layer sequentially arranged. Three metal layers are added on a top of the chip by physical sputtering, so that a heat sink can be welded on the metal layers by a solder layer, and then the heat sink is fixed on the top of the chip; a main component of the solder layer is metal tin, and the metal layer have a higher thermal conductivity than an epoxy adhesive material mounted on a conventional heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.