Glitch reduction in phase shifters
US12101072B2 · kind B2 · utility
0Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2022 |
| Grant date | Sep 24, 2024 |
| Priority date | — |
| Expiry date | Oct 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/25
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.