Logical to physical (L2P) address mapping with fast L2P table load times
US12105621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2022 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Apr 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may detect a memory operation that updates a level two volatile (L2V) entry stored in an L2V table. Each L2V entry in the L2V table may indicate a mapping between a respective logical block address (LBA) and a respective user data physical address in non-volatile memory. The memory operation may cause a mapping between an LBA indicated in the L2V entry and a user data physical address indicated in the L2V entry to become invalid. The memory device may store, in a volatile memory log, an indication of an LBA region that includes the LBA. The memory device may detect that an L2 transfer condition, associated with the volatile memory log, is satisfied. The memory device may copy, from volatile memory to non-volatile memory, every L2V entry that indicates an LBA included in the LBA region based on detecting that the L2 transfer condition is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.