Programmable multi-level data access address generator
US12105625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2022 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Nov 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.