Accelerating relaxed remote atomics on multiple writer operations
US12105957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2022 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.