Power saving floating point multiplier-accumulator with precision-aware accumulation
US12106069B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Jun 4, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which outputs a signed integer form fraction and a maximum exponent. A range estimator forms a possible range of values from the exponent differences and determines an adder precision. The integer form fractions are summed using the adder precision, a sign bit is extracted, and a floating point value is output. Each MAC processor provides its integer form fraction with a precision determined by the MAC processor's exponent difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.