Multiple interfaces for multiple threads of a hardware multi-thread microprocessor
US12106110B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Aug 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are provided for instructions cache system for a hardware multi-thread microprocessor. In some embodiments, a cache controller device includes multiple interfaces connected to a hardware multi-thread microprocessor. A first interface of the multiple interfaces can receive a fetch request from a first execution thread during a first clock cycle. A second interface of the multiple interfaces can receive a fetch request from a second execution thread during a second clock cycle after the first clock cycle. The cache controller device also includes a multiplexer to send first response signals in response to the fetch request from the first execution thread, and also to send second response signals in response to the fetch request from the second execution thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.