Method for manufacturing vertical device
US12107142B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2020 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Dec 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for manufacturing vertical device. The method includes: forming a plurality of first grooves in the front side of the N-type heavily doped layer; forming an N-type lightly doped layer in the plurality of first grooves and on the front side of the N-type heavily doped layer; forming second grooves in the N-type lightly doped layer; forming a P-type semiconductor layer in the second grooves and on the front side of the N-type lightly doped layer; planarizing the P-type semiconductor layer; forming a passivation layer on the planarized structure; forming a third groove in the passivation layer, wherein the third groove has a depth equal to a thickness of the passivation layer; and forming a first electrode and a second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.