Densified gate spacers and formation thereof
US12107145B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Oct 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method includes following steps. Fins are formed over a substrate. A dummy gate structure is across the fins. A spacer layer is deposited over the dummy gate structure. The spacer layer has a first portion in a void of the dummy gate structure and a second portion outside the void of the dummy gate structure. The second portion of the spacer layer is treated to have a different material composition than the first portion of the spacer layer, and is then etched to form gate spacers on sidewalls of the dummy gate structure. An etching process is performed on the dummy gate structure to form a gate trench between the gate spacers. The etching process etches the first portion of the spacer layer at a faster etch rate than etching the gate spacers. A gate structure is formed in the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.