Semiconductor structure, method for forming semiconductor structure and memory
US12108591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Dec 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
A method for forming a semiconductor structure includes: providing a substrate, where a sacrificial layer and an active layer located on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form a groove, where the active layer and the sacrificial layer are divided into a plurality of active regions by the groove; forming a first isolation layer surrounding the active regions in the groove; patterning the active layer in the active regions to form a plurality of separate active patterns, where at least one of side walls or ends of the active patterns is connected to the first isolation layer; removing the sacrificial layer along an opening located between two adjacent one of the active patterns to form a gap between a bottom of the active patterns and the semiconductor substrate; and forming a bit line in the gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.