Validity mapping techniques
US12111769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Nov 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.