Routing structure and method of wafer substrate with standard integration zone for integration on-wafer
US12112115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2023 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jun 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/02381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.