Memory device, the operation method thereof and memory system
US12112802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Apr 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.