Chip interconnection package structure and method

US12112956B2 · kind B2 · utility

Assignee

• Institute of Semiconductors, Guangdong Academy of Sciences · CN

Inventors

• Yao-Chang Wang · Hubei, CN
• Zibai Li · Longbeilingcun, CN
• Yunzhi LING · 流花街道, CN
• Xun XIANG · 流花街道, CN
• Yinhua CUI · 流花街道, CN
• Chuan Hu · Chandler, US
• Zhitao CHEN · 流花街道, CN

Key dates

• Filing date: Feb 8, 2021
• Grant date: Oct 8, 2024
• Expiry date: Jun 30, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/381
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the chip corresponding in projection position.