Semiconductor package and manufacturing method of semiconductor package
US12113022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2020 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a lower encapsulated semiconductor device, a lower redistribution structure, an upper encapsulated semiconductor device, and an upper redistribution structure. The lower redistribution structure is disposed over and electrically connected to the lower encapsulated semiconductor device. The upper encapsulated semiconductor device is disposed over the lower encapsulated semiconductor device and includes a sensor die having a pad and a sensing region, an upper encapsulating material at least laterally encapsulating the sensor die, and an upper conductive via extending through the upper encapsulating material and connected to the lower redistribution structure. The upper redistribution structure is disposed over the upper encapsulated semiconductor device. The upper redistribution structure covers the pad of the sensor die and has an opening located on the sensing region of the sensor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.