Stress-inducing silicon liner in semiconductor devices
US12113118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jul 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.