Strain enhanced SiC power semiconductor device and method of manufacturing
US12113131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2020 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.