Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network

US12113612B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Chunhua Hu · Jiaocheng District, CN
• Venkateswar Reddy Kowkutla · Allen, US
• Eric Hansen · McKinney, US
• Denis Beaudoin · Rowlett, US
• Thomas Anton Leyrer · Geisenhausen, DE

Key dates

• Filing date: Jul 29, 2022
• Grant date: Oct 8, 2024
• Expiry date: Jul 29, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/0083
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.