FeRAM decoupling capacitor
US12114509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Aug 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.