Computational circuit with hierarchical accumulator
US12118060B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Apr 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems relating to computational circuitry are disclosed herein. A disclosed computational circuit includes a math circuit, a first accumulator, and a second accumulator. The first accumulator has a first memory. The second accumulator has a second memory. The first accumulator is communicatively connected to the math circuit and accumulates values from the math circuit in the first memory. The second accumulator is communicatively connected to the first memory and accumulates values from the first memory in the second memory. The first memory is faster and smaller than the second memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.