Deep convolutional network heterogeneous architecture

US12118451B2 · kind B2 · utility

Assignees

• STMicroelectronics SA
• STMicroelectronics International N.V. · NL

Inventors

• Giuseppe Desoli · Cavallasca, IT
• Thomas Boesch · Rovio, CH
• Nitin Chawla · Noida, IN
• Surinder Singh · Fremont, US
• Elio Guidetti · Como, IT
• Fabio Giuseppe DE AMBROGGI · Macherio, IT
• Tommaso Majo · Cascina Uboldi, IT
• Paolo Sergio ZAMBOTTI · Milano, IT

Key dates

• Filing date: Feb 2, 2017
• Grant date: Oct 15, 2024
• Expiry date: Dec 1, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N7/01
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.