Inventor · Noida, IN

Nitin Chawla

33Patents
4h-index
22Co-inventors
59Inventor score

Filing activity: Aug 29, 2005 → Oct 17, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8154335B2 Fail safe adaptive voltage/frequency system Emerging Cross-Sectional Technologies 9 Active
US8037336B2 Spread spectrum clock generation Electricity 7 Active
US7698355B2 Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry Electricity 6 Active
US8269545B2 Fail safe adaptive voltage/frequency system Emerging Cross-Sectional Technologies 4 Active
US7917569B2 Device for implementing a sum of products expression Physics 3 Active
US11094376B2 In-memory compute array with integrated bias elements Electricity 2 Active
US9021324B2 Calibration arrangement Emerging Cross-Sectional Technologies 2 Active
US11474788B2 Elements for in-memory compute Physics 2 Active
US8552765B2 Adaptive multi-stage slack borrowing for high performance error resilient computing Electricity 2 Active
US11984151B2 Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Physics 1 Active
US12087356B2 Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Physics 1 Active
US11605424B2 In-memory compute array with integrated bias elements Electricity 1 Active
US12354644B2 Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Physics 0 Active
US11749343B2 Memory management device, system and method Physics 0 Active
US8994416B2 Adaptive multi-stage slack borrowing for high performance error resilient computing Electricity 0 Active
US12183424B2 Bit-cell architecture based in-memory compute Physics 0 Active
US12176025B2 Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Physics 0 Active
US12406705B2 In-memory computation circuit using static random access memory (SRAM) array segmentation Physics 0 Active
US11726543B2 Computing system power management device, system and method Physics 0 Active
US11360667B2 Tagged memory operated at lower vmin in error tolerant system Emerging Cross-Sectional Technologies 0 Active
US12386506B2 Tagged memory operated at lower VMIN in error tolerant system Emerging Cross-Sectional Technologies 0 Active
US11257543B2 Memory management device, system and method Physics 0 Active
US12292780B2 Computing system power management device, system and method Physics 0 Active
US12243584B2 In-memory compute array with integrated bias elements Electricity 0 Active
US12353341B2 Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.