Efficient soft decoding of error correction code via extrinsic bit information
US12119075B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 16, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Apr 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.