Backside gate contact, backside gate etch stop layer, and methods of forming same
US12119271B1 · kind B1 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Dec 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
Abstract
A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.