Wei-De Ho
9Patents
2h-index
27Co-inventors
43Inventor score
Filing activity: Mar 16, 2015 → Dec 19, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9786569B1 | Overlay measurement and compensation in semiconductor fabrication | Electricity | 3 | Active |
| US9703918B2 | Two-dimensional process window improvement | Physics | 2 | Active |
| US11804410B2 | Thin-film non-uniform stress evaluation | Electricity | 1 | Active |
| US12119271B1 | Backside gate contact, backside gate etch stop layer, and methods of forming same | Electricity | 1 | Active |
| US12120886B2 | Memory device and manufacturing method thereof | Electricity | 0 | Active |
| US12324164B2 | Alignment mark for MRAM device and method | Electricity | 0 | Active |
| US9904163B2 | Cut-mask patterning process for FIN-like field effect transistor (FINFET) device | Electricity | 0 | Active |
| US11749570B2 | Etch monitoring and performing | Electricity | 0 | Active |
| US12374588B2 | Method for evaluating non-uniform stress | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.