Semiconductor package
US12119305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jan 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.