Semiconductor package
US12119306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Apr 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.