Packaging structure of semiconductor chip and formation method thereof
US12119308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2020 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | May 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging structure and fabrication method thereof are provided. The method includes: providing semiconductor chips including soldering pads and metal bumps; providing a base plate, wiring structures, input terminals, and output terminals; mounting the semiconductor chips on the front surface of the base plate inversely, such that each metal bump is connected to a corresponding input terminal; forming a bottom filling layer between a functional surface of each semiconductor chip and the front surface of the base plate; forming a first shielding layer covering a non-functional surface and sidewalls of each semiconductor chip, and covering sidewalls of a corresponding bottom filling layer; forming a second shielding layer on each first shielding layer; forming a plastic encapsulation layer on second shielding layers and on a portion of the base plate between semiconductor chips; and forming external contact structures connected to the output terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.