Memory device and manufacturing method thereof
US12120886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Oct 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.