Contact structure formation for memory devices
US12120963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jun 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
Abstract
A semiconductor structure comprises a bottom electrode contact, and a memory device comprising a bottom electrode disposed on the bottom electrode contact, at least one memory element layer disposed on the bottom electrode, and a top electrode disposed on the at least one memory element layer. A bit line contact is disposed on the top electrode and extends around sides of the memory device and of the bottom electrode contact. An encapsulation layer is disposed between the bit line contact and the sides of the memory device and of the bottom electrode contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.