Semiconductor memory device capable of controlling a floating state of adjacent word lines and an operating method thereof
US12124702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Sep 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.