Memory comprising memory controller configured to determine a logical address of a target zone system and method of operating the memory controller
US12124733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2023 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system according to the present technology may include a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.