Method for manufacturing memory using pseudo bit line structures and sacrificial layers
US12127398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Mar 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a memory includes the following steps. A substrate and bit line contact layers are provided. Pseudo bit line structures are formed at tops of the bit line contact layers. Sacrificial layers filling regions between adjacent bit line structures are formed, and the sacrificial layers are located on side walls of the pseudo bit line structures and side walls of the bit line contact layers. After forming the sacrificial layers, the pseudo bit line structures are removed to form through holes exposing the bit line contact layers. Bit line conductive parts filling the through holes and covering the bit line contact layers are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.