System and method for sharing a cache line between non-contiguous memory areas
US12130736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2023 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Aug 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.