Dynamic logical page sizes for memory devices
US12130747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Dec 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.