Quick charge loss mitigation using two-pass controlled delay
US12131060B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 25, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Sep 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.