Resistive random-access memory (ReRAM) cell optimized for reset and set currents
US12131777B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Apr 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.