Non-volatile memory device
US12131784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Sep 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.