Non-volatile memory device for detecting defects of bit lines and word lines
US12131798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | May 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.