Edge inspection of silicon wafers by image stacking
US12135296B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Jan 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments described herein provide for a defect detection system and method suitable for detecting defects on an edge of a wafer. The method includes placing at least two wafers sequentially on a conveyor. Images of at least the edges of each wafer placed on the conveyor are captured and sent to a controller. A defect detection software combines the images to show the edges of the wafers in a virtual stack. The virtual stack allows for a pattern of defects to be identified. The pattern of defects in close proximity will allow for identification of the defects in the edges of the wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.