System and method for synchronizing processing between a plurality of processors
US12135970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2023 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | May 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and computer program product to synchronize processing across multiple lanes. In a system, a synchronizing interface network controller (SINC) communicates with a plurality of processors. Each processor executes an application having thread(s) of operation. Each processor notifies the SINC when a specific thread is ready to perform a respective operation. The SINC releases the processors to perform the respective operation upon being notified by all processors that the specific thread is ready to perform the respective operation. Each processor is configured to monitor for the release of the processors and to also determine whether sufficient time remains within a time window to perform the respective operation. If insufficient time remains, a processor notifies the SINC that the specific thread is no longer ready to perform the respective operation. If the processors are released by the SINC while sufficient time remains, each processor performs the respective operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.