Patent · US Active

Three-dimensional memory devices and fabricating methods thereof

US12136599B2 · kind B2 · utility

0Cited by
3References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 2, 2022
Grant dateNov 5, 2024
Priority date
Expiry dateOct 15, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/40
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.