Patent · US Active

Translation support for a virtual cache

US12141076B2 · kind B2 · utility

0Cited by

18References

14Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Markus Helms · Eppelheim, DE
Christian Jacobi · West Park, US
Ulrich Mayer · Weißenhorn, DE
Martin Recktenwald · Eppelheim, DE
Johannes C. Reichart · Highland, US
Anthony Saporito · Highland, US
Aaron Tsai · Poughkeepsie, US

Key dates

Filing date	Aug 18, 2023
Grant date	Nov 12, 2024
Priority date	—
Expiry date	Aug 18, 2043

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.