Configurable inter-processor synchronization system
US12141626B2 · kind B2 · utility
1Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Aug 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to an interprocessor synchronization system, comprising a plurality of processors; a plurality of unidirectional notification lines connecting the processors in a chain; in each processor: a synchronization register having bits respectively associated with the notification lines, connected to record the respective states of upstream notification lines, propagated by an upstream processor, and a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.